EE 4OI6 - Engineering Design
	Optional Lab Assignments

Note: These assignments are optional and there are no marks assigned to them. They are meant to give students the opportunity to gain familiarity with VHDL and the UP boards.

Assignment 1

Description: (pdf).

Assignment 2

Description: (pdf).

Dr. Shirani has also posted a number of useful assignments for the other section of CoE 4OI5 which you may also like to try. Please find updated versions here.

Last updated: September 7, 2006.