Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	1,272	21,504	5%
Number of 4 input LUTs	4,920	21,504	22%
Logic Distribution
Number of occupied Slices	2,844	10,752	26%
Number of Slices containing only related logic	2,844	2,844	100%
Number of Slices containing unrelated logic	0	2,844	0%
Total Number 4 input LUTs	5,140	21,504	23%
Number used as logic	4,920
Number used as a route-thru	146
Number used as Shift registers	74
Number of bonded IOBs	156	624	25%
IOB Flip Flops	203
Number of Block RAMs	18	56	32%
Number of MULT18X18s	3	56	5%
Number of GCLKs	7	16	43%
Number of DCMs	4	8	50%
Total equivalent gate count for design	1,269,321
Additional JTAG gate count for IOBs	7,488

Performance Summary
Final Timing Score:	684265	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	3 Failing Constraints