Digital Systems Design course McMaster University - Fall 2006-2011 The material on this page is provided as is, without any warranty or support. Due to lack of bandwidth, inquiry emails will most likely not be replied. The labs and project have been developed using the DE2 board . The original version has been validated with Quartus 7.1 (build 178 06/25/2007 SJ Full Version Service Pack 1 Windows 32-bit), Modelsim-Altera 6.1g (Revision 2006.08), Visual C++ 6.0 (or GCC 3.3.5 under Gentoo kernel 2.6.13-gentoo-r3) and UART - Terminal v1.9b by Bray++. Subsequent updates have kept pace with the latest releases from Quartus and Modelsim. Outline of major topics Programmable logic Design synthesis Design verification Algorithms to hardware Homework problems - solutions (source code) Labs Lab 1 - CAD/Verilog (2006/2007/2008/2009/2010/2011) Solutions to the exercises (2006/2007/2008/2009/2010/2011) Lab 2 - FSM/PS2/LCD (2006/2007/2008/2009/2010/2011) Solutions to the exercises (2006/2007/2008/2009/2010/2011) Lab 3 - VGA/ROM (2006/2007/2008/2009/2010/2011) Solutions to the exercises (2006/2007/2008/2009/2010/2011) Lab 4 - Memories (2006/2007/2008/2009/2010/2011) Solutions to the exercises (2006/2007/2008/2009/2010/2011) Lab 5 - UART/SRAM/VGA (2006/2007/2008/2009/2010/2011) Solutions to the exercises (2006/2007/2008/2009/2010/2011) Project - Hardware Implementation of an Image Decompressor Project description (2006/2007/2008/2009/2010/2011) Behavioral C model (2006/2007/2008/2009/2010/2011) Top-level testbench (2006/2007/2008/2009/2010/2011) Report guidelines (2006/2007/2008/2009/2010/2011) Adam, Henry and Nicola have also worked on the release of source Verilog files for MP3 audio and MPEG2 audio/video decoders. Further details can be found here.

Last changed on January 2, 2012 by     Nicola       Nicola's home        ECE       McMaster University