Publications
- [J12]
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems.
By S. Hessien and M. Hassan.
In ACM Transactions on Embedded Computing Systems (TECS), 2022.@article{hessien2022piscot, title = {PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems}, author = {Hessien, Salah and Hassan, Mohamed}, journal = {ACM Transactions on Embedded Computing Systems (TECS)}, year = {2022}, pdf = {/assets/publications/hessien2022piscot.pdf} }
- [J11]
DISCO: Time-Compositional Cache Coherence for Multi-core Real-Time Embedded Systems.
By M. Hassan.
In IEEE Transactions on Computers, 2022. - [C24]
Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds.
By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
In Euromicro Conference on Real-Time Systems (ECRTS 2022), 2022.@inproceedings{reza_ECRTS_2022, title = {Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds}, author = {Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo}, booktitle = {Euromicro Conference on Real-Time Systems (ECRTS 2022)}, year = {2022}, organization = {Schloss Dagstuhl-Leibniz-Zentrum f{\"u}r Informatik}, pdf = {/assets/publications/reza_ECRTS_2022.pdf} }
- [C23]
Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems.
By M. Hossam and M. Hassan.
In Euromicro Conference on Real-Time Systems (ECRTS 2022), 2022.@inproceedings{hossam2022_pcc_ECRTS, title = {Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems}, author = {Hossam, Mohamed and Hassan, Mohamed}, booktitle = {Euromicro Conference on Real-Time Systems (ECRTS 2022)}, year = {2022}, organization = {Schloss Dagstuhl-Leibniz-Zentrum f{\"u}r Informatik}, pdf = {/assets/publications/hossam2022_pcc_ECRTS.pdf} }
- [C22]
tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge.
By K. Ahmed and M. Hassan.
In IEEE International Conference on Healthcare Informatics (ICHI), 2022.@inproceedings{tinyCare_ICHI_2022, title = {tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge}, author = {Ahmed, Khaled and Hassan, Mohamed}, booktitle = {IEEE International Conference on Healthcare Informatics (ICHI)}, year = {2022}, pdf = {/assets/publications/tinyCare_ICHI_2022.pdf} }
- [C21]
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems.
By K. Asifuzzaman, M. Abuelala, M. Hassan, and F. J. Cazorla.
In IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. pp. 1–9, 2021.@inproceedings{hbm_iccad2021, title = {Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems}, author = {Asifuzzaman, Kazi and Abuelala, Mohamed and Hassan, Mohamed and Cazorla, Francisco J}, booktitle = {IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, pages = {1--9}, year = {2021}, pdf = {/assets/publications/hbm_iccad2021.pdf}, slides = {/assets/publications/hbm_iccad2021_slides.pdf} }
- [C20]
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.
By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
In ACM International Symposium on Memory Systems (MEMSYS), pp. pp. 1–14, 2021.@inproceedings{duomc_memsys2021, author = {Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo}, title = {{DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance}}, booktitle = {{ACM International Symposium on Memory Systems (MEMSYS)}}, year = {2021}, pages = {1--14}, pdf = {/assets/publications/duomc_memsys2021.pdf}, slides = {/assets/publications/duomc_memsys2021_slides.pdf} }
- [C19]
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence.
By R. Pujol, H. Tabani, J. Abella, M. Hassan, and F. J. Cazorla.
In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1162–1165, 2021.@inproceedings{roger_20a_date, title = {{Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence}}, author = {Pujol, Roger and Tabani, Hamid and Abella, Jaume and Hassan, Mohamed and Cazorla, Francisco J}, booktitle = {IEEE Design Automation and Test in Europe (DATE)}, pages = {1162--1165}, year = {2021}, pdf = {/assets/publications/roger_20a_date.pdf}, slides = {/assets/publications/roger_20a_date_slides.pdf} }
- [J10]
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems.
By A. M. Kaushik, M. Hassan, and H. Patel.
In IEEE Transactons on Computers (TC), pp. 1–23 Oct. 2020.@article{pmsi_TC_20, author = {Kaushik, Anirudh M. and Hassan, Mohamed and Patel, Hiren}, title = {{Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems}}, journal = {IEEE Transactons on Computers (TC)}, publisher = {IEEE}, month = oct, pages = {1--23}, pdf = {/assets/publications/pmsi_TC.pdf}, code = {https://gitlab.com/FanusLab/pmsi}, year = {2020} }
- [J9]
MCsim: An Extensible DRAM Memory Controller Simulator.
By R. Mirosanlou, D. Guo, M. Hassan, and R. Pellizzoni.
In IEEE Computer Architecture Letters (CAL), pp. 1–4 2020.@article{rezaCAL, title = {MCsim: An Extensible DRAM Memory Controller Simulator}, author = {Mirosanlou, Reza and Guo, Danlu and Hassan, Mohamed and Pellizzoni, Rodolfo}, journal = {IEEE Computer Architecture Letters (CAL)}, pages = {1--4}, year = {2020}, publisher = {IEEE}, code = {https://github.com/uwuser/MCsim}, pdf = {/assets/publications/reza_MCsim_CAL.pdf} }
- [C18]
Duetto: Latency Guarantees at Minimal Performance Cost.
By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1–6, 2020.@inproceedings{reza_DATE_20, author = {Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo}, title = {{Duetto: Latency Guarantees at Minimal Performance Cost}}, booktitle = {{IEEE Design Automation and Test in Europe (DATE)}}, year = {2020}, pages = {1--6}, month = dec, pdf = {/assets/publications/reza_20b_date.pdf}, slides = {/assets/publications/reza_20b_date_slides.pdf} }
- [C17]
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence.
By R. Pujol, H. Tabani, J. Abella, M. Hassan, and F. J. Cazorla.
In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1–4, 2020.@inproceedings{roger_DATE_20, author = {Pujol, Roger and Tabani, Hamid and Abella, Jaume and Hassan, Mohamed and Cazorla, Francisco J.}, title = {{Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence}}, booktitle = {{IEEE Design Automation and Test in Europe (DATE)}}, year = {2020}, pages = {1--4}, month = dec, pdf = {/assets/publications/roger_20a_date.pdf}, slides = {/assets/publications/roger_20a_date_slides.pdf} }
- [C16]
The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications.
By S. Hessien and M. Hassan.
In IEEE Real-Time Systems Symposium (RTSS), pp. pp. 1–12, 2020.@inproceedings{salah_piscot_rtss, author = {Hessien, Salah and Hassan, Mohamed}, title = {{The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications}}, booktitle = {{IEEE Real-Time Systems Symposium (RTSS)}}, year = {2020}, pages = {1--12}, month = oct, pdf = {/assets/publications/piscot_20_rtss.pdf}, slides = {/assets/publications/piscot_20_rtss_slides.pdf}, code = {https://gitlab.com/FanosLab/piscot-and-msi-split-bus} }
- [C15]
Discriminative Coherence: Balancing Performance and Latency Bounds in Data-sharing Multi-Core Real-Time Systems.
By M. Hassan.
In Euromicro Conference on Real-Time Systems (ECRTS), pp. pp. 1–22, 2020.@inproceedings{hassan_20a_ecrts, author = {Hassan, Mohamed}, title = {Discriminative Coherence: Balancing Performance and Latency Bounds in Data-sharing Multi-Core Real-Time Systems}, booktitle = {{Euromicro Conference on Real-Time Systems (ECRTS)}}, year = {2020}, pages = {1--22}, month = jul, pdf = {/assets/publications/hassan_20a_ecrts.pdf}, slides = {/assets/publications/hassan_20a_ecrts_slides.pdf} }
- [C14]
Analysis of Memory-Contention in Heterogeneous COTS MPSoCs.
By M. Hassan and R. Pellizzoni.
In Euromicro Conference on Real-Time Systems (ECRTS), pp. pp. 1–22, 2020.Outstanding Paper Award@inproceedings{hassan_20b_ecrts, author = {Hassan, Mohamed and Pellizzoni, Rodolfo}, title = {Analysis of Memory-Contention in Heterogeneous COTS MPSoCs}, booktitle = {{Euromicro Conference on Real-Time Systems (ECRTS)}}, year = {2020}, pages = {1--22}, month = jul, pdf = {/assets/publications/hassan_20b_ecrts.pdf}, slides = {/assets/publications/hassan_20b_ecrts_slides.pdf}, award = {Outstanding Paper Award}, code = {https://gitlab.com/FanusLab/memory-contention-analysis} }
- [C13]
DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2020.@inproceedings{reza_20_drambulism, title = {DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining}, author = {Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo}, booktitle = {{IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}}, year = {2020}, pdf = {/assets/publications/reza_20_drambulism.pdf}, slides = {/assets/publications/reza_20_drambulism_slides.pdf} }
- [TR4]
APPENDIX TO DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
Technical Report #FANUS-TR-2020-01, 2020.@techreport{reza_20_drambulism_trep, author = {Mirosanlou, Reza and Hassan, Mohamed and Pellizzoni, Rodolfo}, title = {{APPENDIX TO DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining}}, number = {FANUS-TR-2020-01}, pages = {1--7}, pdf = {/assets/publications/reza_20_drambulism_trep.pdf}, year = {2020} }
- [J8]
Reduced latency DRAM for multi-core safety-critical real-time systems.
By M. Hassan.
In Real-Time Systems, pp. 1–36 2019.Special Issue of RTSS’18 Outstanding Papers@article{hassan2019reduced, title = {Reduced latency DRAM for multi-core safety-critical real-time systems}, author = {Hassan, Mohamed}, journal = {Real-Time Systems}, pages = {1--36}, year = {2019}, publisher = {Springer}, pdf = {/assets/publications/hassan2019reduced.pdf}, slides = {/assets/publications/hassan2018off_slides.pdf}, award = {Special Issue of RTSS'18 Outstanding Papers} }
- [C12]
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. pp. 1–11, 2019.@inproceedings{niv_19_pendulum_rtss, author = {Sritharan, Nivedita and Kaushik, Anirudh M. and Hassan, Mohamed and Patel, Hiren}, title = {Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems}, booktitle = {{proceedings of IEEE Real-Time Systems Symposium (RTSS)}}, year = {2019}, pages = {1--11}, month = dec, pdf = {/assets/publications/niv_19_pendulum_rtss.pdf}, code = {https://gitlab.com/FanusLab/pendulum-coherence} }
- [C11]
Managing DRAM Interference in Mixed CriticalityEmbedded Systems.
By M. Hassan.
In International Conference on Microelectronics (ICM), pp. pp. 1–5, 2019.@inproceedings{hassan_dram_icm, title = {{Managing DRAM Interference in Mixed CriticalityEmbedded Systems}}, author = {Hassan, Mohamed}, booktitle = {International Conference on Microelectronics (ICM)}, pages = {1--5}, year = {2019}, pdf = {/assets/publications/hassan_dram_icm.pdf}, slides = {/assets/publications/hassan_dram_icm_slides.pdf}, organization = {IEEE} }
- [TR3]
PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems.
By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
Technical Report #FANUS-TR-2019-01, Dec-2019.@techreport{niv_19_pendulum_trep, author = {Sritharan, Nivedita and Kaushik, Anirudh M. and Hassan, Mohamed and Patel, Hiren}, title = {{PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems}}, month = dec, number = {FANUS-TR-2019-01}, pages = {1--7}, pdf = {/assets/publications/niv_19_pendulum_trep.pdf}, code = {https://gitlab.com/FanusLab/pendulum-coherence}, year = {2019} }
- [J7]
Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems.
By M. Hassan and R. Pellizzoni.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no., 11 pp. 2323–2336 2018.@article{hassan2018boundingTCAD, title = {Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems}, author = {Hassan, Mohamed and Pellizzoni, Rodolfo}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, volume = {37}, number = {11}, pages = {2323--2336}, year = {2018}, pdf = {/assets/publications/hassan2018boundingTCAD.pdf}, slides = {/assets/publications/hassan2018boundingEMSOFT_slides.pdf}, publisher = {IEEE} }
- [J6]
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
By M. Hassan, A. M. Kaushik, and H. D. Patel.
In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, no., 5 pp. 90:1–90:25 2018.@article{hassan2018reverse, author = {Hassan, Mohamed and Kaushik, Anirudh M. and Patel, Hiren D.}, title = {Exposing Implementation Details of Embedded {DRAM} Memory Controllers through Latency-based Analysis}, journal = {{ACM Transactions on Embedded Computing Systems (TECS)}}, volume = {17}, number = {5}, pages = {90:1--90:25}, pdf = {/assets/publications/hassan2018reverse.pdf}, slides = {/assets/publications/hassan_15_reverse_slides.pdf}, year = {2018} }
- [C10]
On the off-chip memory latency of real-time systems: Is ddr dram really the best option?
By M. Hassan.
In 2018 IEEE Real-Time Systems Symposium (RTSS), pp. pp. 495–505, 2018.Best Paper Award@inproceedings{hassan2018off, title = {On the off-chip memory latency of real-time systems: Is ddr dram really the best option?}, author = {Hassan, Mohamed}, booktitle = {2018 IEEE Real-Time Systems Symposium (RTSS)}, pages = {495--505}, year = {2018}, pdf = {/assets/publications/hassan2018off.pdf}, slides = {/assets/publications/hassan2018off_slides.pdf}, award = {Best Paper Award}, organization = {IEEE} }
- [C9]
Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems.
By M. Hassan and R. Pellizzoni.
In ACM SIGBED International Conference on Embedded Software (EMSOFT), 2018.Best Paper Award@inproceedings{hassan2018boundingEMSOFT, title = {Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems}, author = {Hassan, Mohamed and Pellizzoni, Rodolfo}, booktitle = {ACM SIGBED International Conference on Embedded Software (EMSOFT)}, year = {2018}, pdf = {/assets/publications/hassan2018boundingEMSOFT.pdf}, slides = {/assets/publications/hassan2018boundingEMSOFT_slides.pdf}, award = {Best Paper Award}, publisher = {ACM} }
- [TR2]
Variability windows for predictable DDR controllers, a technical report.
By M. Hassan.
Technical Report #FANUS-TR-2018-01, Dec-2018. - [J5]
Hourglass: Predictable time-based cache coherence protocol for dual-critical multi-core systems.
By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
In arXiv preprint arXiv:1706.07568, 2017.@article{niv_17_hourglass, title = {Hourglass: Predictable time-based cache coherence protocol for dual-critical multi-core systems}, author = {Sritharan, Nivedita and Kaushik, Anirudh M and Hassan, Mohamed and Patel, Hiren}, journal = {arXiv preprint arXiv:1706.07568}, year = {2017} }
- [J4]
A Comparative Study of Predictable DRAM Controllers.
By D. Guo, M. Hassan, R. Pellizzoni, and H. Patel.
In ACM Transactions on Embedded Computing Systems (TECS), Nov. 2017.@article{guo2017Comp, author = {Guo, Danlu and Hassan, Mohamed and Pellizzoni, Rodolfo and Patel, Hiren}, issue = {}, journal = {{ACM Transactions on Embedded Computing Systems (TECS)}}, volume = {}, number = {}, month = nov, year = {2017}, issn = {}, pages = {}, articleno = {}, numpages = {25}, title = {{A Comparative Study of Predictable DRAM Controllers}}, pdf = {/assets/publications/guo2017Comp.pdf} }
- [J3]
Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities.
By M. Hassan.
In IEEE Design & Test, vol. 35, no., 4 pp. 47–55 2017.@article{hassan2017heterogeneous, title = {Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities}, author = {Hassan, Mohamed}, journal = {IEEE Design \& Test}, volume = {35}, number = {4}, pages = {47--55}, year = {2017}, pdf = {/assets/publications/hassan2017heterogeneous.pdf}, publisher = {IEEE} }
- [J2]
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
By M. Hassan and H. Patel.
In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), no., 99 pp. 1–14 2017.@article{hassan_17_mcxplore_tcad, author = {Hassan, Mohmaed and Patel, Hiren}, journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, title = {{MCXplore: Automating the Validation Process of DRAM Memory Controller Designs}}, year = {2017}, number = {99}, pages = {1--14}, keywords = {Benchmark testing;Computational modeling;Delays;Model checking;Random access memory;Space exploration;DRAM;memory controller;model checking;testing;validation;verification}, doi = {10.1109/TCAD.2017.2705123}, issn = {0278-0070}, pdf = {/assets/publications/hassan_17_mcxplore_tcad.pdf}, slides = {/assets/publications/hassan_17_mcxplore_slides.pdf}, month = {} }
- [J1]
PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
By M. Hassan, H. Patel, and R. Pellizzoni.
In ACM Transactions on Embedded Computing Systems (TECS), vol. 16 pp. 100:1–100:28 May 2017.@article{hassan_17_tecs_pmc, author = {Hassan, Mohamed and Patel, Hiren and Pellizzoni, Rodolfo}, issue = {}, journal = {{ACM Transactions on Embedded Computing Systems (TECS)}}, volume = {16}, number = {4}, month = may, year = {2017}, issn = {1539-9087}, pages = {100:1--100:28}, articleno = {100}, numpages = {28}, title = {{PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality}}, pdf = {/assets/publications/hassan_17_tecs_pmc.pdf} }
- [C8]
Predictable cache coherence for multi-core real time systems.
By M. Hassan, A. Kaushik, and H. Patel.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 1–12, 2017.@inproceedings{hassan_17_pmsi, author = {Hassan, Mohamed and Kaushik, Anirudh and Patel, Hiren}, booktitle = {{proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}}, month = apr, pages = {1--12}, publisher = {IEEE}, title = {{Predictable cache coherence for multi-core real time systems}}, code = {https://gitlab.com/FanusLab/pmsi}, year = {2017}, pdf = {/assets/publications/hassan_17_pmsi.pdf}, slides = {/assets/publications/hassan_17_pmsi_slides.pdf} }
- [C7]
Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems.
By M. Hassan and H. Patel.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 1–11, 2016.@inproceedings{hassan_16_carb, author = {Hassan, Mohamed and Patel, Hiren}, booktitle = {{proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}}, date-added = {2014-09-27 19:04:05 +0000}, date-modified = {2014-09-27 19:06:55 +0000}, month = apr, pages = {1--11}, publisher = {IEEE}, title = {{Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems}}, year = {2016}, pdf = {/assets/publications/hassan_16_carb.pdf}, slides = {/assets/publications/hassan_16_carb_slides.pdf} }
- [C6]
MCXplore: An Automated Framework for Validating Memory Controller Designs.
By M. Hassan and H. Patel.
In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1357–1362, 2016.\textbfAcceptance rate: 24%@inproceedings{hassan_16_mcxplore, author = {Hassan, Mohamed and Patel, Hiren}, booktitle = {{IEEE Design Automation and Test in Europe (DATE)}}, date-added = {2014-09-27 19:04:05 +0000}, date-modified = {2014-09-27 19:06:55 +0000}, month = sep, pages = {1357--1362}, numpages = {6}, publisher = {IEEE}, note = {\textbf{Acceptance rate: 24\%}}, title = {{MCXplore: An Automated Framework for Validating Memory Controller Designs}}, code = {https://gitlab.com/FanusLab/mcxplore}, year = {2016}, pdf = {/assets/publications/hassan_16_mcxplore.pdf}, slides = {/assets/publications/hassan_16_mcxplore_slides.pdf} }
- [TR1]
MCXplore v.1: An Open-Source Tool to validate and evaluate Memory Controllers, A Manual.
By M. Hassan and H. Patel.
Technical Report #FANUS-TR-2016-01, Oct-2016.@techreport{hassan_mcxplore_manual, author = {Hassan, Mohamed and Patel, Hiren}, title = {{MCXplore v.1: An Open-Source Tool to validate and evaluate Memory Controllers, A Manual}}, month = oct, number = {FANUS-TR-2016-01}, pages = {1--7}, pdf = {/assets/publications/hassan_mcxplore_manual.pdf}, year = {2016} }
- [C5]
Reverse-engineering Embedded Memory Controllers through Latency-based analysis.
By M. Hassan, A. M. Kaushik, and H. Patel.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 297–306, 2015.@inproceedings{hassan_15_reverse, author = {Hassan, Mohamed and Kaushik, Anirudh M. and Patel, Hiren}, booktitle = {{proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}}, date-modified = {2014-09-27 19:03:41 +0000}, month = dec, pages = {297--306}, title = {{Reverse-engineering Embedded Memory Controllers through Latency-based analysis}}, year = {2015}, pdf = {/assets/publications/hassan_15_reverse.pdf}, slides = {/assets/publications/hassan_15_reverse_slides.pdf} }
- [C4]
A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems.
By M. Hassan, H. Patel, and R. Pellizzoni.
In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 307–316, 2015.@inproceedings{hassan_15_pmc, author = {Hassan, Mohamed and Patel, Hiren and Pellizzoni, Rodolfo}, booktitle = {{proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}}, month = oct, pages = {307--316}, title = {{A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems}}, year = {2015}, pdf = {/assets/publications/hassan_15_pmc.pdf} }
- [C3]
Efficient decimal leading zero anticipator designs.
By M. H. Amin, A. M. Eltantawy, A. F. Khedr, H. A. H. Fahmy, and A. A. Naguib.
In 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), pp. pp. 139–143, 2011.@inproceedings{amin2011efficient, title = {Efficient decimal leading zero anticipator designs}, author = {Amin, Mohamed H and Eltantawy, Ahmed M and Khedr, Alhassan F and Fahmy, Hossam AH and Naguib, Ahmed A}, booktitle = {2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)}, pages = {139--143}, year = {2011}, pdf = {/assets/publications/amin2011efficient.pdf}, organization = {IEEE} }
- [C2]
Testing of first and second order Delta-Sigma converters for catastrophic faults.
By M. H. Amin, M. B. Abdelhalim, and H. H. Amer.
In 2011 20th European Conference on Circuit Theory and Design (ECCTD), pp. pp. 889–892, 2011.@inproceedings{amin2011testing, title = {Testing of first and second order Delta-Sigma converters for catastrophic faults}, author = {Amin, MH and Abdelhalim, Mohamed B and Amer, HH}, booktitle = {2011 20th European Conference on Circuit Theory and Design (ECCTD)}, pages = {889--892}, year = {2011}, pdf = {/assets/publications/amin2011testing.pdf}, organization = {IEEE} }
- [C1]
Generalization of Logic Picture-based power estimation tool.
By M. H. Amin, M. F. Fouda, A. M. Eltantawy, M. B. Abdelhalim, and H. H. Amer.
In 2010 International Conference on Energy Aware Computing, pp. pp. 1–4, 2010.@inproceedings{amin2010generalization, title = {Generalization of Logic Picture-based power estimation tool}, author = {Amin, MH and Fouda, MF and Eltantawy, AM and Abdelhalim, MB and Amer, HH}, booktitle = {2010 International Conference on Energy Aware Computing}, pages = {1--4}, year = {2010}, pdf = {/assets/publications/amin2010generalization.pdf}, organization = {IEEE} }