Cinque Terre

Mohamed Hassan

News


Sept 11, 2019

ACCEPTED PAPER: My single-authored paper entitled "Reduced Latency DRAM for Multi-Core Safety-Critical Real-Time Systems" is accepted in the Real-Time Systems Journal, A special issue for the outstanding RTSS'18 papers

Sept 9, 2019

ACCEPTED PAPER: My paper with Nivedita Sritharan, Anirudh M. Kaushik and Hiren Patel entitled "Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems" is accepted in IEEE Real-Time Systems Symposium (RTSS), 2019

Aug 31, 2019

Service: I am serving in the Program Committee of RTAS'20

May 11, 2019

Service: I am serving in the Program Committee of EMSOFT, WiP-track, which is part of ESWEEK

May 1, 2019

POSITION: I will be joining ECE, McMaster University starting from Summer, 2019

April 16, 2019

AWARD: I have been awarded the Discovery Launch Supplement Award from NSERC

April 12, 2019

SERVICE: I am attending CPSWeek , and I will be chairing the Parallel Tasks Session in IEEE RTAS'19 .

Dec 16, 2018

AWARD: My paper entitled "On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?" received the Best PAPER AWARD in the IEEE Real-Time Systems Symposium (RTSS), 2018.

Dec 11, 2018

INVITED TALK: It was my pleasure to give a talk about MPSoCs for Mixed Criticality Systems in the 6th International Workshop on Mixed Criticality Systems slides of the talk can be downloaded from here: WMC_talk_2018.pdf

Short Bio

I am currently an Assistant Professor at the ECE Department, McMaster University. Before joining McMaster, I was an Assistant Professor at University of Guelph. Before that, I was a SoC R&D engineer at Intel. I obtained my PhD from University of Waterloo in 2017 and my MSc. From Cairo University in 2012.

Interests:

  • Real-time embedded systems
  • Cyber-Physical Systems (CPS) and Internet-of-Things (IoT)
  • Mixed criticality systems for automotive and avionics
  • Timing analysis
  • Simulation-based validation and performance testing
  • Computer architecture (with special interest in memory systems for multi-core architectures)
  • Security at the architecture/hardware level
  • Compilers and code optimizations

Publications


Journals:

    2019

  • [J8] Reduced Latency DRAM for Multi-Core Safety-Critical Real-Time Systems
    By Hassan, M.
    Springer Real-Time Systems Journal (TIME) , 2019.
    Special Issue for Outstanding RTSS'18 Papers

    2018

  • [J7] Exposing Implementation Details of Embedded Memory Controllers through Latency-based Analysis
    By Hassan, M., Kaushik, A. and Patel, H.
    ACM Transactions on Embedded Computing Systems (TECS), 2018.

  • [J6] Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
    By Hassan, M. and Pellizzoni, R.
    accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Special issue of ESWEEK, 2018

    2017

  • [J5] Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities
    By Hassan, M.
    In IEEE Design and Test Magazine, 2017

  • [J4] A Comparative Study of Predictable DRAM Controllers
    By Guo, D., Hassan, M., Pellizzoni, R., and Patel, H.
    In ACM Transactions on Embedded Computing Systems (TECS), 2017

  • [J3] MCXplore: Automating the Validation Process of DRAM Memory Controller Designs
    By Hassan, M., Patel, H.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1–14, 2017.

    2016

  • [J2] PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–25, 2016.


Journals under review:

  • [J1] Towards a Full-Chain Standard-compliant Decimal Floating Point Computing System
    By Hassan, M., Eltantawy, A. and Fahmy, H.
    Submitted to IEEE Transactions on Computers (TC), under review


Journals under submission:

  • [J8] CArb: a Requirement- and Criticality-aware Bus Arbiter for Multi- core Mixed Criticality Systems
    By Hassan, M., Patel, H.
    In IEEE Transactions on Computers (TC), pp. 1–14

  • [J9] The Cache Coherence Challenge in Multi-Core Real-Time Systems
    By Hassan, M., Kaushik, A., Patel, H.
    In ACM Transactions on Embedded Computing Systems (TECS), pp. 1–25.

Conferences:

    2019

  • [C12] Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems"
    By Sritharan, N., Kaushik, A., Hassan, M. and Patel, H.
    In IEEE Real Time Systems Symposium (RTSS) , 2019

    2018

  • [C11] On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?
    By Hassan, M.
    In IEEE Real Time Systems Symposium (RTSS) , 2018
    Best Paper Award

  • [C10] Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
    By Hassan, M. and Pellizzoni, R.
    In The ACM SIGBED International Conference on Embedded Software (EMSOFT), ESWEEK, 2018
    Best Paper Award

    2017

  • [C9] HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems
    By Sritharan, N., Kaushik, A., Hassan, M. and Patel, H.
    arXiv:1706.07568v1, 2017

  • [C8] Predictable cache coherence for multi-core real time systems
    By Hassan, M., Kaushik, A. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, 2017.

    2016

  • [C7] Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems
    By Hassan, M. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–11, 2016.

  • [C6] MCXplore: An Automated Framework for Validating Memory Controller Designs
    By Hassan, M. and Patel, H.
    In proceedings of IEEE Design Automation and Test in Europe (DATE),, pp. 1–6, 2016.

    2015

  • [C5] Reverse-engineering Embedded Memory Controllers through Latency-based analysis
    By Hassan, M., Kaushik, A. and Patel, H.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–10, 2015.

  • [C4] A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems
    By Hassan, M., Patel, H. and Pellizzoni, R.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–10, 2015.

    2011

  • [C3] Efficient Decimal Leading Zero Anticipator Designs
    By Amin, M., ElTantawy, A., Khedr, A., Fahmy, H.
    In IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 1–5, 2011.

  • [C2] Testing of First and Second Order Delta- Sigma Converters for Catastrophic Faults
    By Amin, M., Abdelhalim, M., Amer, H.
    In IEEE European Conference on Circuit Theory and Design (ECCTD), pp. 1–4, 2011.

  • [C1] Generalization of Logic Picture-based Power Estimation Tool
    By Amin, M., Fouda, M., Eltantawy, A., Abdelhalim, M., Amer, H.
    In IEEE International Conference on Energy Aware Computing (ICEAC) , pp. 1–4, 2011.

Technical Reports, Manuals, and Theses:

  • [R6] Variability Windows for Predictable DDR Controllers, A Technical Report
    By Hassan, M.
    Technical Report, 2018.

  • [R6] Predictable Shared Memory Resources for Multi-Core Real-Time Systems
    By Hassan, M.
    PhD Thesis, 2017.

  • [R5] Checking for Timing Violations in DRAM Memory Controllers
    By Hassan, M. and Patel, H.
    UW Technical Report , pp. 1–10, 2016.

  • [R4] MCXplore v.1: An Open-Source Tool to validate and evaluate Memory Controllers, A Manual
    By Hassan, M. and Patel, H.
    UW Technical Report, pp. 1–14, 2016.

  • [R3] Latency-based Analysis of DRAM Memory Controllers
    By Hassan, M., Kaushik, A. and Patel, H.
    UW Technical Report, pp. 1–14, 2014.

  • [R2] Auto Transformation of MIPS ISA to URISC Turing-complete ISA
    By Hassan, M. and Patel, H.
    UW Technical Report, pp. 1–4, 2013.

  • [R1] Including a Decimal Floating Point Unit In an Open-Source Processor and Patching Its Compiler"
    By Hassan, M.
    MSc. Thesis, 2012.

EDUCATION

Mar 2017 PhD in Computer Engineering

University of Waterloo

Group: Computer Architecture and Embedded Systems Research (CAESR)
Thesis Title: Predictable Shared Memory Resources for Multi-Core Real-Time Embedded Systems

May 2012 MSc. in Computer Engineering

Cairo University

Thesis Title: Including a Decimal Floating Point Unit in an Open-Source Processor and Patching its Compiler

May 2009 BSc. in Electronics and Electrical Communications Engineering

Cairo University

Thesis Title: A Portable Mobile Intensity Level Meter and Its Software Interface

AWARDS

April 2019 Discovery Launch Supplement Award

Natural Sciences and Engineering Research Council of Canada (NSERC)


Dec 2018 IEEE TCRTS Best Paper Award

IEEE Real-Time Systems Symposium (RTSS)


Oct 2018 ACM SIGBED Best Paper Award

ACM SIGBED International Conference on Embedded Software (EMSOFT), Embedded Systems Week


Dec 2016 Doctoral Thesis Completion Award

University of Waterloo


Sep2012-Aug2015 (7 times) International Doctoral Student Award

University of Waterloo


Feb2014, Feb2017 (2 times) Faculty of Engineering Award (FOE)

University of Waterloo


Sep2012-Apr2017 UW Graduate Research Studentship

University of Waterloo


Jan2010 Outstanding Teaching Assistant Award

Cairo University


Sep2009-Aug2012 Cairo University T.A./R.A. Fellowship

Cairo University


May2009 The ITAC Graduation Project Award

Egyptian Ministry of Information Technology


Sep2004-May2019 Undergraduate Highest Distinction Award

Cairo University


TEACHING EXPERIENCE

Jul2019-Now Main Instructor

McMaster University, ECE

  • COMPENG-2SH4 Principles of Programming

Aug2018-Jun2019 Main Instructor

University of Guelph, SOE

  • ENGG3380 Computer Organization
  • ENGG4540 Advanced Computer Architecture

Jan2013-Dec2016 Teaching Assistant

University of Waterloo, ECE

  • ECE222 Digital Computers
  • ECE429 Computer Architecture
  • ECE351 Compiler Construction

Jan2014-May2014 Lab Instructor

University of Waterloo, ECE

  • ECE351 Compiler Construction

Sep2009-Aug2012 Lab Instructor

Cairo University, EECE

  • Computer Architecture: A third-year undergraduate lab
  • Microcontrollers: A fourth-year undergraduate lab
  • Introduction Matlab: A second-year undergraduate lab.
  • Signal processing using Matlab: A second-year undergraduate lab
  • Digital Circuits: A first-year undergraduate lab
  • Assembly Language: A first-year undergraduate lab

Sep2009-Aug2012 Teaching Assistant

Cairo University, EECE

  • ELC303A Computer Architecture
  • ELC 201A Basics of Analog and Digital Electronic
  • ELC 203 Microprocessor Design
  • ELC303B Data Structure via C++
  • Object Oriented Programming
  • ELC 443 Computer Networks
  • Digital Design using VHDL: A graduate course.

Feb2010-May2010 Teaching Assistant

Cairo University, AERE

  • Electronic Circuits: A third-year undergraduate course at Aerospace Department

Feb2010-May2010 Lab Instructor

American University in Cairo, ECE

  • EENG221 Circuits and Electronics
  • EENG218 Logic Design

Feb2010-May2010 Lab Instructor

American University in Cairo, PHY

  • PHYS112 Electricity and Magnetism

Feb2010-May2010 Teaching Assistant

American University in Cairo, ECE

  • EENG525 Data Signal Processing(DSB): A graduate course.
  • EENG221 Circuits and Electronics

Feb2010-May2010 Teaching Assistant

American University in Cairo, MATH

  • MACT304 Numerical Methods using C++

TEACHING CERTIFICATES

Fundamentals of University Teaching Program (FUT)

University of Waterloo

  • CTE217 Teaching Methods
  • CTE006 Teaching Large Classes
  • CTE202 Effective Lesson Plans
  • CTE196 Teaching Philosophy Statements

Center for Learning and Teaching (CLT)

American University in Cairo

  • Incorporating feedback into your own teaching context
  • Making Thinking Visible: Learning and Teaching with Concept/MindMaps
  • Motivating students: Bridging the gap between student needs and teacher expectations

Faculty and Leadership Development Center (FLDC)

Cairo University

  • Modern Technologies in Teaching
  • Team Management
  • Communication Skills in Different Learning Methods
  • Time Management in the Academic Life

INDUSTRIAL EXPERIENCE

May2017-Now SoC R&D Engineer

Intel


Oct2014-Jun2015 SoC Computer Architecture Testing and Performance Intern Engineer

Qualcomm

  • Validating and performance-testing the new generation of Qualcomm's memory controllers equipped in future SnapDragon chips.
  • Exploring the design space for multi-channel DRAMs Namely, exploring the effectiveness of dual- and quad-channel memory systems

May2010-Oct2010 Digital design lab instructor/consultant

Mentor Graphics

  • Trained fresh graduates on digital design methodologies and RTL modelling

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May2008-Aug2008 Hardware Intern Engineer

Al-Wadi Computer Technologies


May2007-Aug2007 Telecommunications Intern Engineer

Telecom Egypt


May2006-Aug2006 Telecommunications and Control Intern Engineer

The National Authority for Tunnels (N.A.T)


May2006-Aug2006 Part-time Softwar Engineer

Arab Group of Computers (AGC)

I worked as a part-time trainee software developer. During my working periods, I have developed a variety of commercial products including:
  • A complete healthcare platform for a set of hospitals in Sudan
  • An inventory management platform
  • A store billing framework with par-code scanning and automatic report generation

PROFESSIONAL SERVICE

Journals:

Reviewer

ACM Transactions on Cyber-Physical Systems (TCPS)
.
March2019-Present

Reviewer

IEEE Design and Test Magazine (D&T)
.
March2017-Present

Reviewer

Elsevier Journal of System Architecture (JSA)
.
Nov 2015-Present

Reviewer

ACM Transactions on Embedded Computing Systems (TECS)
.
Feb 2015-Present

Conferences:

Program Committee (PC) Memeber,

The ACM SIGBED International Conference on Embedded Software (EMSOFT): Work-in-Progress (WiP) track
.
2019

Program Committee (PC) Memeber

the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS): Main Program, Artifcat Evaluation (AE), and Brief Presentations (BP) Track
.
2019

Program Committee (PC) Memeber

the IEEE Real-Time Systems Symposium Artifact Evaluation (RTSS-AE)
.
2018

Program Committee (PC) Memeber

the IEEE Forum on Specification & Design Languages (FDL)
.
2018

External Reviewer

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
.
2018

External Reviewer

ACM Design Automation Conference (DAC)
.
2017

External Reviewer

IEEE International High-Level Design Validation and Test Workshop (HLDVT)
.
2016

External Reviewer

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
.
2016

External Reviewer

International Conference on Computer Aided Design (ICCAD)
.
2015

External Reviewer

Hifa Verification Conference (HVC)
.
2013

External Reviewer

ACM-IEEE International Conference on Formal Methods and Models for System Design (MEM- OCODE)
.
2013

News


ACCEPTED PAPER: My single-authored paper entitled "Reduced latency DRAM for multi-core safety-critical real-time systems" is accepted in the Real-Time Systems Journal, A special issue for the outstanding RTSS'18 papers

Sept 11, 2019

ACCEPTED PAPER: My paper with Nivedita Sritharan, Anirudh M. Kaushik and Hiren Patel entitled "Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems" is accepted in IEEE Real-Time Systems Symposium (RTSS), 2019

Sept 9, 2019

Service: I am serving in the Program Committee of RTAS'20

Aug 31, 2019

Service: I am serving in the Program Committee of EMSOFT'19, WiP-track, which is part of ESWEEK

May 11, 2019

NEW POSITION: I will be joining ECE, McMaster University starting from Summer, 2019

May 1, 2019

AWARD: I have been awarded the Discovery Launch Supplement Award from NSERC

April 16, 2019

SERVICE: I am attending CPSWeek , and I will be chairing the Parallel Tasks Session in IEEE RTAS'19 .

April 12, 2019

AWARD: My paper entitled "On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?" received the Best PAPER AWARD in the IEEE Real-Time Systems Symposium (RTSS), 2018.

Dec 16, 2018

INVITED TALK: It was my pleasure to give a talk about MPSoCs for Mixed Criticality Systems in the 6th International Workshop on Mixed Criticality Systems slides of the talk can be downloaded from here: WMC_talk_2018.pdf

Dec 11, 2018

AWARD: My paper with Rodolfo Pellizzoni entitled "Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems" has received the BEST PAPER AWARD in the ACM SIGBED International Conference on Embedded Software (EMSOFT), which is part of the IEEE/ACM Embedded Systems Week (ESWEEK)

OCT 4, 2018

SERVICE: I am servicing as a Program Committee (PC) member in the 25th IEEE Real-Time and Embedded Technology and Applications Symposium. RTAS is a top-tier conference with a focus on systems research related to embedded systems and time-sensitive systems (of any size). The broad scope of RTAS'19 ranges from traditional hard real-time systems to embedded systems without explicit timing requirements, including latency-sensitive systems with informal or soft real-time requirements.

Sept 3, 2018

ACCEPTED PAPER: My paper with Anirudh M. Kaushik and Hiren Patel entitled "Exposing Implementation Details of Embedded Memory Controllers through Latency-based Analysis" is accepted in ACM Transactions on Embedded Computing Systems (TECS)

Aug 28, 2018

SERVICE: I am servicing as a Program Committee (PC) member in the IEEE Real-Time Systems Symposium Artifact Evaluation (RTSS-AE). RTSS is is the premier conference in the field of real time systems, presenting innovations with respect to both theory and practice. RTSS-AE offers authors the opportunity to show guarantees of reproducibility and validation given by the community for the experiments and data reported in their paper.

Aug 20, 2018

AWARD: My paper entitled "On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?" is chosen to receive the OUTSTANDING PAPER AWARD in the IEEE Real-Time Systems Symposium (RTSS), 2018.

Aug 10, 2018

ACCEPTED PAPER: My paper entitled "On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?" is accepted in IEEE Real-Time Systems Symposium (RTSS), 2018.

July 20, 2018

ACCEPTED PAPER: My paper with Rodolfo Pellizzoni entitled "Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems" is accepted in The ACM SIGBED International Conference on Embedded Software (EMSOFT), ESWEEK and is going to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

July 01, 2018

SERVICE: I am servicing as a Program Committee (PC) member in the IEEE Forum on Specification & Design Languages (FDL). FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods, and tools for the design of electronic systems.

Mar 29, 2018

INDUSTRY: Intel finally announces Cyclone 10 FPGAs for Internet-of-Things (IoT). I had the pleasure to be the leading engineer for the external memory interface subsystem of these high-bandwidth and low-cost devices.

Feb 17, 2018

ACCEPTED PAPER: My paper with Danlu Guo, Rodolfo Pellizzoni, and Hiren Patel entitled "A Comparative Study of Predictable DRAM Controllers" is accepted in the ACM Transactions on Embedded Computing Systems (TECS)

Nov 3, 2017

ACCEPTED PAPER: My paper entitled "Heterogeneous MPSoCs for Mixed Criticality Systems: Challenges and Opportunities" is accepted in IEEE Design and Test Magazine

Oct 24, 2017

CONTACT

mohamed(dot)hassan(at)mcmaster(dot)ca