Mohamed Hassan

Mohamed Hassan

Assistant Professor

Publications

By Year By Type

    2022

  1. [J12] PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems.
    By S. Hessien and M. Hassan.
    In ACM Transactions on Embedded Computing Systems (TECS), 2022.
  2. [J11] DISCO: Time-Compositional Cache Coherence for Multi-core Real-Time Embedded Systems.
    By M. Hassan.
    In IEEE Transactions on Computers, 2022.
  3. [C24] Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds.
    By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
    In Euromicro Conference on Real-Time Systems (ECRTS 2022), 2022.
  4. [C23] Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems.
    By M. Hossam and M. Hassan.
    In Euromicro Conference on Real-Time Systems (ECRTS 2022), 2022.
  5. [C22] tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge.
    By K. Ahmed and M. Hassan.
    In IEEE International Conference on Healthcare Informatics (ICHI), 2022.

    6. 2021

  6. [C21] Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems.
    By K. Asifuzzaman, M. Abuelala, M. Hassan, and F. J. Cazorla.
    In IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. pp. 1–9, 2021.
  7. [C20] DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.
    By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
    In ACM International Symposium on Memory Systems (MEMSYS), pp. pp. 1–14, 2021.
  8. [C19] Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence.
    By R. Pujol, H. Tabani, J. Abella, M. Hassan, and F. J. Cazorla.
    In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1162–1165, 2021.

    9. 2020

  9. [J10] Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems.
    By A. M. Kaushik, M. Hassan, and H. Patel.
    In IEEE Transactons on Computers (TC), pp. 1–23 Oct. 2020.
  10. [J9] MCsim: An Extensible DRAM Memory Controller Simulator.
    By R. Mirosanlou, D. Guo, M. Hassan, and R. Pellizzoni.
    In IEEE Computer Architecture Letters (CAL), pp. 1–4 2020.
  11. [C18] Duetto: Latency Guarantees at Minimal Performance Cost.
    By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
    In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1–6, 2020.
  12. [C17] Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence.
    By R. Pujol, H. Tabani, J. Abella, M. Hassan, and F. J. Cazorla.
    In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1–4, 2020.
  13. [C16] The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications.
    By S. Hessien and M. Hassan.
    In IEEE Real-Time Systems Symposium (RTSS), pp. pp. 1–12, 2020.
  14. [C15] Discriminative Coherence: Balancing Performance and Latency Bounds in Data-sharing Multi-Core Real-Time Systems.
    By M. Hassan.
    In Euromicro Conference on Real-Time Systems (ECRTS), pp. pp. 1–22, 2020.
  15. [C14] Analysis of Memory-Contention in Heterogeneous COTS MPSoCs.
    By M. Hassan and R. Pellizzoni.
    In Euromicro Conference on Real-Time Systems (ECRTS), pp. pp. 1–22, 2020.
    Outstanding Paper Award
  16. [C13] DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
    By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
    In IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2020.
  17. [TR4] APPENDIX TO DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
    By R. Mirosanlou, M. Hassan, and R. Pellizzoni.
    Technical Report #FANUS-TR-2020-01, 2020.

    18. 2019

  18. [J8] Reduced latency DRAM for multi-core safety-critical real-time systems.
    By M. Hassan.
    In Real-Time Systems, pp. 1–36 2019.
    Special Issue of RTSS’18 Outstanding Papers
  19. [C12] Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
    By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
    In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. pp. 1–11, 2019.
  20. [C11] Managing DRAM Interference in Mixed CriticalityEmbedded Systems.
    By M. Hassan.
    In International Conference on Microelectronics (ICM), pp. pp. 1–5, 2019.
  21. [TR3] PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems.
    By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
    Technical Report #FANUS-TR-2019-01, Dec-2019.

    22. 2018

  22. [J7] Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems.
    By M. Hassan and R. Pellizzoni.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no., 11 pp. 2323–2336 2018.
  23. [J6] Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
    By M. Hassan, A. M. Kaushik, and H. D. Patel.
    In ACM Transactions on Embedded Computing Systems (TECS), vol. 17, no., 5 pp. 90:1–90:25 2018.
  24. [C10] On the off-chip memory latency of real-time systems: Is ddr dram really the best option?
    By M. Hassan.
    In 2018 IEEE Real-Time Systems Symposium (RTSS), pp. pp. 495–505, 2018.
    Best Paper Award
  25. [C9] Bounding DRAM interference in COTS heterogeneous MPSoCs for mixed criticality systems.
    By M. Hassan and R. Pellizzoni.
    In ACM SIGBED International Conference on Embedded Software (EMSOFT), 2018.
    Best Paper Award
  26. [TR2] Variability windows for predictable DDR controllers, a technical report.
    By M. Hassan.
    Technical Report #FANUS-TR-2018-01, Dec-2018.

    27. 2017

  27. [J5] Hourglass: Predictable time-based cache coherence protocol for dual-critical multi-core systems.
    By N. Sritharan, A. M. Kaushik, M. Hassan, and H. Patel.
    In arXiv preprint arXiv:1706.07568, 2017.
  28. [J4] A Comparative Study of Predictable DRAM Controllers.
    By D. Guo, M. Hassan, R. Pellizzoni, and H. Patel.
    In ACM Transactions on Embedded Computing Systems (TECS), Nov. 2017.
  29. [J3] Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities.
    By M. Hassan.
    In IEEE Design & Test, vol. 35, no., 4 pp. 47–55 2017.
  30. [J2] MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
    By M. Hassan and H. Patel.
    In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), no., 99 pp. 1–14 2017.
    doi
  31. [J1] PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality.
    By M. Hassan, H. Patel, and R. Pellizzoni.
    In ACM Transactions on Embedded Computing Systems (TECS), vol. 16 pp. 100:1–100:28 May 2017.
  32. [C8] Predictable cache coherence for multi-core real time systems.
    By M. Hassan, A. Kaushik, and H. Patel.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 1–12, 2017.

    33. 2016

  33. [C7] Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems.
    By M. Hassan and H. Patel.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 1–11, 2016.
  34. [C6] MCXplore: An Automated Framework for Validating Memory Controller Designs.
    By M. Hassan and H. Patel.
    In IEEE Design Automation and Test in Europe (DATE), pp. pp. 1357–1362, 2016.
    \textbfAcceptance rate: 24%
  35. [TR1] MCXplore v.1: An Open-Source Tool to validate and evaluate Memory Controllers, A Manual.
    By M. Hassan and H. Patel.
    Technical Report #FANUS-TR-2016-01, Oct-2016.

    36. 2015

  36. [C5] Reverse-engineering Embedded Memory Controllers through Latency-based analysis.
    By M. Hassan, A. M. Kaushik, and H. Patel.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 297–306, 2015.
  37. [C4] A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems.
    By M. Hassan, H. Patel, and R. Pellizzoni.
    In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. pp. 307–316, 2015.

    38. 2011

  38. [C3] Efficient decimal leading zero anticipator designs.
    By M. H. Amin, A. M. Eltantawy, A. F. Khedr, H. A. H. Fahmy, and A. A. Naguib.
    In 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), pp. pp. 139–143, 2011.
  39. [C2] Testing of first and second order Delta-Sigma converters for catastrophic faults.
    By M. H. Amin, M. B. Abdelhalim, and H. H. Amer.
    In 2011 20th European Conference on Circuit Theory and Design (ECCTD), pp. pp. 889–892, 2011.

    40. 2010

  40. [C1] Generalization of Logic Picture-based power estimation tool.
    By M. H. Amin, M. F. Fouda, A. M. Eltantawy, M. B. Abdelhalim, and H. H. Amer.
    In 2010 International Conference on Energy Aware Computing, pp. pp. 1–4, 2010.