Computer-Aided Design and Test Research Group (CADT)
Current group members: Nicola Nicolici, Henry Ko, Adam
Kinsman, David Leung, Ehab Anis, Kaveh Elizeh and Roomi Sahi. Thesis supervised or co-supervised by Nicola: Theo Gonciari (Ph.D. 2003) - Low-cost test for core-based
system-on-a-chip Paul Rosinger (Ph.D. 2003) - Power-conscious scan-based test of
digital VLSI circuits Bai Hong Fang (M.A.Sc. 2003) - Embedded memory BIST for
systems-on-a-chip Ho Fai Ko (M.A.Sc. 2004) - Functional scan design at RTL David Lemstra (M.A.Sc. 2005) – A high level synthesis approach
for reduced interconnects and fault tolerance Adam Kinsman (M.A.Sc. 2005) – Embedded deterministic test for
systems-on-a-chip Qiang Xu (Ph.D. 2005) – Solutions for
emerging problems in modular system-on-a-chip testing David Leung (M.A.Sc. 2007) – SAT-based ATPG for digital integrated
circuits based on multiple observations Books: N.
Nicolici
and B.M. Al-Hashimi, Power-constrained
testing of VLSI circuits, Kluwer Academic Publishers (Frontiers
in Electronic Testing
Series), February 2003, ISBN 1-4020-7235-X. Papers: IET/IEEE conference and journal papers can be downloaded from IEEEXplore. Releases: Test scheduling for core-based SOCs - a prototype tool, developed by Qiang Xu as part of his doctoral research. A modified version of the ITC'02 benchmarks (including random functional interconnect), is also available here. Source Verilog files for MP3 audio and MPEG2 audio/video decoding are available here. |
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Last changed on August 21, 2008 by Nicola Nicola's home Electrical and Computer Engineering McMaster University |