Computer Engineering 2DI4
Academic year 2013-2014, term 1
Final Exam Coverage:
Ch1.6, Ch2.1~2.7, Ch4.1~4.7, Ch5.1~5.4, Ch6.1~6.5, Ch7.1~7.11, Ch8.1~8.3
Q8.1, Q8.3, Q8.5, Q8.6, Q8.15, Q8.29
Q7.3, Q7.4, Q7.6, Q7.13, Q7.18, Q7.24, Q7.33, Q7.35
Q6.3, Q6.5, Q6.6, Q6.14, Q6.29, Q6.30
Q5.1~5.5, Q5.12, Q5.13, Q5.21, Q.22
Answers: Q1:5; Q2:5; Q3:3; Q4:2; Q5:1; Q6:4; Q7:3; Q8: 3; Q9: 2; Q10: 4; Q14: 1; Q15: 4; Q17: 4; Q18: 4; Q19: 4; Q20: 4; Q21: 3;
Lab. 4 will start on Nov. 11 (Monday)
Mark distribution of 2nd midterm
Mark distribution of 1st midterm
Darwish, A. - email@example.com, Office hours: Wed. 9:00~11:00am, ITB 239
Deng, X. - firstname.lastname@example.org, Office hours: Tue. 3:30~5:30pm. ITB A103
Thompson, J -email@example.com, Office hours: Wed. 10:30~12:30am. ITB A201
Li, Zhenhao - firstname.lastname@example.org, Office hours: Tue. 3:30~5:30pm. ITB A103
Sivakumaran, L. -email@example.com, Office hours: Mon. 9:30~10:30am., Wed. 9:00~10:00am. ITB A202
Rezaee Kaviani - firstname.lastname@example.org Office hours: Wed. 3:30~5:30pm, ITB A103
Instructor: Dr. Xiaolin Wu
Rooms: ITB-A315 10:30-11:20 in MDCL/1105
Office hours: Tuesdays and Thursdays 3:30 ~ 5:30 pm.
Tutorials: Tuesdays 11:30-12:20 or Wednesdays 13:30-14:20 in T13/125
Course Objectives: To understand the principles and techniques of logic design and their relation to digital devices and computer organization.
List of Main Topics:
Unsigned binary numbers, base conversions, representation of negative numbers, binary arithmetic
Boolean Algebra, Digital Logic and Electrical Properties of Logic Gates
Introduction to Boolean algebra, truth tables and logic gates
Propagation delay, signal levels, noise margins, fan-in, fan-out, glitches
Combinational Circuit Design
Circuit simplification using K-maps, ripple carry adders, carry look-ahead adders
Design of basic building blocks such as decoders, multiplexers, encoders, comparators
Implementation technology and programmable logic
Complementary metal-oxide semiconductors (CMOS) technology
Programmable logic arrays (PLA), field programmable gate arrays (FPGA), read only memories (ROM)
Introduction to hardware description languages (VHDL)
Sequential Circuit Design
Latches, flip-flops, counters, shift registers, state diagrams and tables
Control logic implementation using finite state machines (FSM)
Introduction to Computer Organization
Central processing unit (CPU), arithmetic and logic unit (ALU), register files
Register transfer logic; microoperations and microprograms
This Web site will be the primary source for course-related information. You should check this site frequently for updates including lab descriptions and schedule, manufacturers' data sheets, problem sets and solutions, course announcements, etc.
“Fundamentals of Digital Logic with VHDL Design, third edition”, by Brown & Vranesic.
Laboratories are designed to enhance and supplement the lecture material. ATTENDANCE AT ALL LAB SESSIONS IS REQUIRED. The laboratory is located in ITB/143 and will be available for your use on one afternoon from 14:30 until 17:20 on alternate weeks. For the exact dates please check the lab schedule, which is posted on the course website. You will work in groups of 2. The five lab sessions are:
1. Logic Gates
2. Combinational Logic Design
3. Programmable Logic
4. Sequential Logic Design
5. Design of a Register File and Datapath
Labs will start in the week of September 22. The lab material and the lab schedule will be available on the course website. If you have not been assigned a lab section by the Office of the Registrar, then you should email the tutorial TA (Hoda Rezaee, email@example.com) between September 10th and 16th and provide her a list of three preferred lab sections where you wish to be assigned. In order to change your lab section you must bring to the tutorial TA some formal documentation in the week of September 16. The documentation must prove why you need to change your lab section (e.g., letter from an employer, proof of conflict with other courses, letter from a medical doctor, ...). Only after your documentation has been verified you may change your lab section.
In addition to the final exam, there will be two compulsory midterm tests on October 10 and November 4 (dates are subject to change). Students who miss the midterms, and who have a valid reason, will be accommodated. Those who do not have a valid excuse will be assessed zero for the midterm components of the final grade.
Labs 10 %
Midterm Test #1 20 %
Midterm Test #2 20%
Final Examination 50 %
NO calculators will be allowed during tests and examinations. To pass the course you must obtain at least 50% on the final examination, attend all laboratory sessions and obtain at least 8 of the 10 points allocated to labs.
The instructor reserves the right to choose the format (i.e. written or oral) of any deferred midterm or exam in this course.
Please note that announcements concerning any type of graded material may be in any format (e.g., announcements may be made only in class). Students are responsible for completing the graded material regardless of whether they received the announcement or not. What this means is that if you skip class and an announcement for a quiz, lab, test etc. is made in that class, then you are still responsible for that material. If you miss it, then you get zero.
Academic dishonesty will be taken very seriously. Any copying of labs etc. will be reported to the Office of Academic Integrity. Both the copyee and the copyor will be reported. On the first offence, the standard penalty is a zero on the work in question. Subsequent offences are much more serious: the student is typically assigned an F in the course, with a transcript notation indicating the F is for academic dishonesty.
"The instructor and university reserve the right to modify elements of the course during the term. The university may change the dates and deadlines for any or all courses in extreme circumstances. If either type of modification becomes necessary, reasonable notice and communication with the students will be given with explanation and the opportunity to comment on changes. It is the responsibility of the student to check their McMaster email and course websites weekly during the term and to note any changes."
“The Faculty of Engineering is concerned with ensuring an environment that is free of all adverse discrimination. If there is a problem, that cannot be resolved by discussion among the persons concerned, individuals are reminded they should contact the Departmental Chair, the Sexual Harassment Officer or the Human Rights Consultant, as soon as possible.”
“Students are reminded that they should read and comply with the Statement on Academic Ethics and the Senate Resolutions on Academic Dishonesty as found in the Senate Policy Statements distributed at registration and available at the senate office.”
"Academic dishonesty consists of misrepresentation by deception or by other fraudulent means and can result in serious consequences, e.g. the grade of zero on an assignment, loss of credit with a notation on the transcript (notation reads: "Grade of F assigned for academic dishonesty"), and/or suspension or expulsion from the university. It is your responsibility to understand what constitutes academic dishonesty. For information on the various kinds of academic dishonesty please refer to the Academic Integrity Policy, specifically Appendix 3, located at http://www.mcmaster.ca/senate/academic/ac_integrity.htm
The following illustrates only three forms of academic dishonesty:
1. Plagiarism, e.g. the submission of work that is not one's own or for which other credit has been obtained
2. Improper collaboration in group work. (E.g., using previous year’s lab reports).
3. Copying or using unauthorized aids in tests and examinations.